module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A = 1'b0;
    parameter B = 1'b1; 
    reg state;
    reg next_state;

    always @(posedge clk or posedge areset) begin
        if(areset) begin
            state <= B;
        end
        else begin
            case(state)
                A:	if(in) begin
                    	state <= A;
                	end
                	else begin
                        state <= B;
                    end
                B:	if(in) begin
                    	state <= B;
                	end
                	else begin
                        state <= A;
                    end
            endcase
        end
    end
    
    assign out = state;

endmodule
